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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 120 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? non-volatile program and data memories ? 2/4/8k byte of in-system programmable program memory flash (attiny25/45/85) endurance: 10,000 write/erase cycles ? 128/256/512 by tes in-system programmable eeprom (attiny25/45/85) endurance: 100,000 write/erase cycles ? 128/256/512 bytes internal sram (attiny25/45/85) ? programming lock for self-program ming flash program and eeprom data security ? peripheral features ? 8-bit timer/counter with pr escaler and two pwm channels ? 8-bit high speed timer/counte r with separate prescaler 2 high frequency pwm outputs with separate output compare registers programmable dead time generator ? usi ? universal seri al interface with start condition detector ? 10-bit adc 4 single ended channels 2 differential adc channel pairs wi th programmable gain (1x, 20x) temperature measurement ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? external and internal interrupt sources ? low power idle, adc noise reduction, and power-down modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit ? internal calibrated oscillator ? i/o and packages ? six programmable i/o lines ? 8-pin pdip, 8-pin soic and 20-pad qfn/mlf ? operating voltage ? 1.8 - 5.5v for attiny25/45/85v ? 2.7 - 5.5v for attiny25/45/85 ? speed grade ? attiny25/45/85v: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 10 mhz @ 2.7 - 5.5v ? attiny25/45/85: 0 - 10 mhz @ 2.7 - 5.5v, 0 - 20 mhz @ 4.5 - 5.5v ? industrial temperature range ? low power consumption ? active mode: 1 mhz, 1.8v: 300 a ? power-down mode: 0.1 a at 1.8v 8-bit microcontroller with 2/4/8k bytes in-system programmable flash attiny25/v* attiny45/v attiny85/v* summary *preliminary 2586js?avr?12/06
2 2586js?avr?12/06 attiny25/45/85 1. pin configurations figure 1-1. pinout attiny25/45/85 1 2 3 4 8 7 6 5 (pcint5/reset/adc0/dw) pb5 (pcint3/xtal1/clki/oc1b/adc3) pb3 (pcint4/xtal2/clko/oc1b/adc2) pb4 gnd vcc pb2 (sck/usck/scl/adc1/t0/int0/pcint2) pb1 (miso/do/ain1/oc0b/oc1a/pcint1) pb0 (mosi/di/sda/ain0/oc0a/oc1a/aref/pcint0) pdip/soic 1 2 3 4 5 qfn/mlf 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 dnc dnc gnd dnc dnc dnc dnc dnc dnc dnc note: bottom pad should be soldered to ground. dnc: do not connect (pcint5/reset/adc0/dw) pb5 (pcint3/xtal1/clki/oc1b/adc3) pb3 dnc dnc (pcint4/xtal2/clko/oc1b/adc2) pb4 vcc pb2 (sck/usck/scl/adc1/t0/int0/pcint2) dnc pb1 (miso/do/ain1/oc0b/oc1a/pcint1) pb0 (mosi/di/sda/ain0/oc0a/oc1a/aref/pcint0)
3 2586js?avr?12/06 attiny25/45/85 2. overview the attiny25/45/85 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructio ns in a single clock cycle, the attiny25/45/85 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent program counter internal oscilla tor watchdog timer stack pointer program flash sram mcu control register general purpose registers instruction register timer/ counter0 serial universal interface timer/ counter1 instruction decoder data dir. reg.port b data register port b programming logic timing and control mcu status register status register alu port b drivers pb0-pb5 vcc gnd control lines 8-bit databus z adc / analog comparator interrupt unit data eeprom calibrated oscillators y x reset
4 2586js?avr?12/06 attiny25/45/85 registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the attiny25/45/85 provides the following featur es: 2/4/8k byte of in-system programmable flash, 128/256/512 bytes eeprom, 128/256/256 bytes sram, 6 general purpose i/o lines, 32 general purpose working registers, one 8-bit timer/counter with compare modes, one 8-bit high speed timer/counter, universal serial interface, internal and external interrupts, a 4-channel, 10-bit adc, a programmable watc hdog timer with in ternal oscillato r, and three so ftware select- able power saving modes. the idle mode stops the cpu while allowing the sram, timer/counter, adc, analog comparator, and interrupt system to continue functioning. the power-down mode saves the register contents, di sabling all chip functions until the next inter- rupt or hardware reset. the adc noise reduction mode stops the cpu and all i/o modules except adc, to minimize switch ing noise during adc conversions. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be re-programmed in-system through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the avr core. the attiny25/45/85 avr is supported with a full suite of program and system development tools including: c compilers, macro as semblers, program debugger/simu lators, in-circu it emulators, and evaluation kits. 2.2 pin descriptions 2.2.1 vcc supply voltage. 2.2.2 gnd ground. 2.2.3 port b (pb5..pb0) port b is a 6-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various s pecial features of the attiny25/45/85 as listed on page 61 . on the attiny25 device the programmable i/o ports pb3 and pb4 (pins 2 and 3) are exchanged in the attiny15 compatibility mode for supporting the backwar d compatibility with attiny15. 2.2.4 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 23-3 on page 170 . shorter pulses are not guaranteed to generate a reset.
5 2586js?avr?12/06 attiny25/45/85 3. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr.
6 2586js?avr?12/06 attiny25/45/85 4. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f sreg i t h s v n z c page 7 0x3e sph ? ? ? ? ? ? sp9 sp8 page 10 0x3d spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 10 0x3c reserved ? 0x3b gimsk ? int0 pcie ? ? ? ? ? page 51 0x3a gifr ? intf0 pcif ? ? ? ? ? page 52 0x39 timsk ? ocie1a ocie1b ocie0a ocie0b toie1 toie0 ? page 84 / page 106 0x38 tifr ? ocf1a ocf1b ocf0a ocf0b tov1 tov0 ? page 84 0x37 spmcsr ? ? ? ctpb rflb pgwrt pgers spmen page 148 0x36 reserved ? 0x35 mcucr bods pud se sm1 sm0 bodse isc01 isc00 page 37 , page 51 , page 65 , 0x34 mcusr ? ? ? ? wdrf borf extrf porf page 44 , 0x33 tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 page 82 0x32 tcnt0 timer/counter0 page 83 0x31 osccal oscillator calibration register page 31 0x30 tccr1 ctc1 pwm1a com1 a1 com1a0 cs13 cs12 cs11 cs10 page 92 , page 103 0x2f tcnt1 timer/counter1 page 94 , page 105 0x2e ocr1a timer/counter1 output compare register a page 94 , page 105 0x2d ocr1c timer/counter1 output compare register c page 95 , page 106 0x2c gtccr tsm pwm1b com1b1 com1b0 foc1b foc1a psr1 psr0 page 79 , page 93 , page 0x2b ocr1b timer/counter1 output compare register b page 95 0x2a tccr0a com0a1 com0a0 com0b1 com0b0 ? wgm01 wgm00 page 79 0x29 ocr0a timer/counter0 ? output compare register a page 83 0x28 ocr0b timer/counter0 ? output compare register b page 84 0x27 pllcsr lsm ? ? ? ? pcke plle plock page 97 , page 107 0x26 clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 32 0x25 dt1a dt1ah3 dt1ah2 dt1ah1 dt 1ah0 dt1al3 dt1al2 dt1al1 dt1al0 page 109 0x24 dt1b dt1bh3 dt1bh2 dt1bh1 dt 1bh0 dt1bl3 dt1bl2 dt1bl1 dt1bl0 page 110 0x23 dtps1 - - - - - - dtps11 dtps10 page 109 0x22 dwdr dwdr[7:0] page 145 0x21 wdtcr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 page 44 0x20 prr ? prtim1 prtim0 prusi pradc page 36 0x1f eearh eear8 page 19 0x1e eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 19 0x1d eedr eeprom data register page 19 0x1c eecr ? ? eepm1 eepm0 eerie eempe eepe eere page 20 0x1b reserved ? 0x1a reserved ? 0x19 reserved ? 0x18 portb ? ? portb5 portb4 portb3 portb2 portb1 portb0 page 65 0x17 ddrb ? ? ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 65 0x16 pinb ? ? pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 65 0x15 pcmsk ? ? pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 page 52 0x14 didr0 ? ? adc0d adc2d adc3d adc1d ain1d ain0d page 125 , page 143 0x13 gpior2 general purpose i/o register 2 page 9 0x12 gpior1 general purpose i/o register 1 page 9 0x11 gpior0 general purpose i/o register 0 page 9 0x10 usibr usi buffer register page 119 0x0f usidr usi data register page 118 0x0e usisr usisif usioif usipf usi dc usicnt3 usicnt2 usicnt1 usicnt0 page 119 0x0d usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc page 120 0x0c reserved ? 0x0b reserved ? 0x0a reserved ? 0x09 reserved ? 0x08 acsr acd acbg aco aci acie ? acis1 acis0 page 124 0x07 admux refs1 refs0 adlar refs2 mux3 mux2 mux1 mux0 page 138 0x06 adcsra aden adsc adate adif adie adps2 adps1 adps0 page 140 0x05 adch adc data register high byte page 141 0x04 adcl adc data register low byte page 141 0x03 adcsrb bin acme ipr ? ? adts2 adts1 adts0 page 124 , page 142 0x02 reserved ? 0x01 reserved ? 0x00 reserved ?
7 2586js?avr?12/06 attiny25/45/85 note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specified bit, and can theref ore be used on registers contai ning such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only.
8 2586js?avr?12/06 attiny25/45/85 5. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1
9 2586js?avr?12/06 attiny25/45/85 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
10 2586js?avr?12/06 attiny25/45/85 6. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. 3. for speed vs. v cc ,see figure 23.3 on page 168 6.1 attiny25 speed (mhz) (3) power supply ordering code (2) package (1) operational range 10 1.8 - 5.5v attiny25v-10pu attiny25v-10su ATTINY25V-10MU 8p3 8s2 20m1 industrial (-40 c to 85 c) 20 2.7 - 5.5v attiny25-20pu attiny25-20su attiny25-20mu 8p3 8s2 20m1 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s2 8-lead, 0.209" wide, plastic gull-wing small outline (eiaj soic) 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no -lead/micro lead frame package (qfn/mlf)
11 2586js?avr?12/06 attiny25/45/85 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. 3. for speed vs. v cc ,see figure 23.3 on page 168 6.2 attiny45 speed (mhz) (3) power supply ordering code (2) package (1) operational range 10 1.8 - 5.5v attiny45v-10pu attiny45v-10su attiny45v-10mu 8p3 8s2 20m1 industrial (-40 c to 85 c) 20 2.7 - 5.5v attiny45-20pu attiny45-20su attiny45-20mu 8p3 8s2 20m1 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s2 8-lead, 0.209" wide, plastic gull-wing small outline (eiaj soic) 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no -lead/micro lead frame package (qfn/mlf)
12 2586js?avr?12/06 attiny25/45/85 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. 3. for speed vs. v cc ,see figure 23.3 on page 168 6.3 attiny85 speed (mhz) (3) power supply ordering code (2) package (1) operational range 10 1.8 - 5.5v attiny85v-10pu attiny85v-10su attiny85v-10mu 8p3 8s2 20m1 industrial (-40 c to 85 c) 20 2.7 - 5.5v attiny85-20pu attiny85-20su attiny85-20mu 8p3 8s2 20m1 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s2 8-lead, 0.209" wide, plastic gull-wing small outline (eiaj soic) 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no -lead/micro lead frame package (qfn/mlf)
13 2586js?avr?12/06 attiny25/45/85 7. packaging information 7.1 8p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
14 2586js?avr?12/06 attiny25/45/85 7.2 8s2 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s 2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 4/7/06 8s2 d common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs are not included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 0 8 e 1.27 bsc 4 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d side view s i d e v i e w
15 2586js?avr?12/06 attiny25/45/85 7.3 20m1 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 9 51 3 1 title drawing no. r rev. 20m1 , 20-p a d, 4 x 4 x 0. 8 mm body, le a d pitch 0.50 mm, a 20m1 10/27/04 2.6 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) a 0.70 0.75 0. 8 0 a1 ? 0.01 0.05 a2 0.20 ref b 0.1 8 0.2 3 0. 3 0 d 4.00 b s c d2 2.45 2.60 2.75 e 4.00 b s c e2 2.45 2.60 2.75 e 0.50 b s c l 0. 3 5 0.40 0.55 side view pin 1 id pin #1 notch (0.20 r) bottom view top view note: reference jedec s t a nd a rd mo-220, fig . 1 (saw singulation) wggd-5. common dimensions (unit of me asu re = mm) symbol min nom max note d e e a2 a1 a d2 e2 0.0 8 c l 1 2 3 b 1 2 3
16 2586js?avr?12/06 attiny25/45/85 8. errata 8.1 errata attiny25 the revision letter in this section refers to the revision of the attiny25 device. 8.1.1 rev c no known errata 8.1.2 rev b ? reading eeprom at low frequency may no t work for frequencies below 900 khz 1. reading eeprom at low frequency may not work for frequencies below 900 khz reading data from the eeprom at low internal clock frequency may result in wrong data read. problem fix/workaround avoid using the eeprom at cl ock frequency below 900khz. 8.1.3 rev a not sampled.
17 2586js?avr?12/06 attiny25/45/85 8.2 errata attiny45 the revision letter in this section refers to the revision of the attiny45 device. 8.2.1 rev e no known errata 8.2.2 rev d ? reading eeprom at low frequency may no t work for frequencies below 900 khz 1. reading eeprom at low frequency may not work for frequencies below 900 khz reading data from the eeprom at low internal clock frequency may result in wrong data read. problem fix/workaround avoid using the eeprom at cl ock frequency below 900khz. 8.2.3 rev b and c ? pll not locking ? eeprom read from applicat ion code does not work in lock bit mode 3 ? reading eeprom at low frequency may no t work for frequencies below 900 khz ? timer counter 1 pwm output generation on oc1b- xoc1b does not work correctly 1. pll not locking when at frequencies below 6. 0 mhz, the pll will not lock problem fix / workaround when using the pll, run at 6.0 mhz or higher. 2. eeprom read from applic ation code does not work in lock bit mode 3 when the memory lock bits lb2 and lb1 are programmed to mode 3, eeprom read does not work from the application code. problem fix/work around do not set lock bit protection mode 3 when the application code needs to read from eeprom. 3. reading eeprom at low frequency may not work for frequencies below 900 khz reading data from the eeprom at low internal clock frequency may result in wrong data read. problem fix/workaround avoid using the eeprom at cl ock frequency below 900khz. 4. timer counter 1 pwm output generation on oc1b ? xoc1b does not work correctly timer counter1 pwm output oc1b-xoc1b does no t work correctly. only in the case when the control bits, com1b1 and com1b0 are in the same mode as com1a1 and com1a0, respectively, the oc1b-xoc1b output works correctly. problem fix/work around the only workaround is to use same control setting on com1a(1:0) and com1b(1:0) con- trol bits, see table 14-4 in the data sheet. the problem has been fixed for tiny45 rev d.
18 2586js?avr?12/06 attiny25/45/85 8.2.4 rev a ? too high power down power consumption ? debugwire looses communication when single stepping into interrupts ? pll not locking ? eeprom read from applicat ion code does not work in lock bit mode 3 ? reading eeprom at low frequency may no t work for frequencies below 900 khz 1. too high power down power consumption three situations will lead to a too high power down power consumption. these are: ? an external clock is selected by fuses, bu t the i/o port is still enabled as an output. ? the eeprom is read before entering power down. ? vcc is 4.5 volts or higher. problem fix / workaround ? when using external clock, avoid setting the clock pin as output. ? do not read the eeprom if power do wn power consumption is important. ? use vcc lower than 4.5 volts. 2. debugwire looses communication when single stepping into interrupts when receiving an inte rrupt during single st epping, debugwire will loose communication. problem fix / workaround ? when singlestepping, disable interrupts. ? when debugging interrupts, use breakpoints within the interrupt routine, and run into the interrupt. 3. pll not locking when at frequencies below 6. 0 mhz, the pll will not lock problem fix / workaround when using the pll, run at 6.0 mhz or higher. 4. eeprom read from applic ation code does not work in lock bit mode 3 when the memory lock bits lb2 and lb1 are programmed to mode 3, eeprom read does not work from the application code. problem fix/work around do not set lock bit protection mode 3 when the application code needs to read from eeprom. 5. reading eeprom at low frequency may not work for frequencies below 900 khz reading data from the eeprom at low internal clock frequency may result in wrong data read. problem fix/workaround avoid using the eeprom at cl ock frequency below 900khz.
19 2586js?avr?12/06 attiny25/45/85 8.3 errata attiny85 the revision letter in this section refers to the revision of the attiny85 device. 8.3.1 rev b no known errata. 8.3.2 rev a ? reading eeprom at low frequency may no t work for frequencies below 900 khz 1. reading eeprom at low frequency may not work for frequencies below 900 khz reading data from the eeprom at low internal clock frequency may result in wrong data read. problem fix/workaround avoid using the eeprom at cl ock frequency below 900khz.
20 2586js?avr?12/06 attiny25/45/85 9. datasheet revision history 9.1 rev. 2586j-12/06 1. updated ?low power consumption? on page 1 . 2. updated description of instruction length in ?architectural overview? , starting on page 6 . 3. updated flash size in ?in-system re-programmable flash program memory? on page 14 . 4. updated cross-references in sections ?atomic byte programming? , ?erase? and ?write? , starting on page 16 . 5. updated ?atomic byte programming? on page 16 . 6. updated ?internal pll for fast peripheral clock generation - clkpck? on page 23 . 7. replaced single clocking system figure with two: figure 7-2 and figure 7-3 on page 23 . 8. updated table 7-1 on page 24 , table 7-4 on page 26 and table 7-6 on page 28 . 9. updated ?calibrated internal rc oscillator? on page 27 . 10. updated table 7-11 on page 29 . 11. updated ?osccal ? oscillator calibrat ion register? on page 31 . 12. updated ?clkpr ? clock prescale register? on page 32 . 13. updated ?power-down mode? on page 35 . 14. updated ?bit 0? in ?prr ? power reduction register? on page 38 . 15. added footnote to table 9-3 on page 46 . 16. updated table 12-5 on page 64 . 17. deleted ?bits 7, 2? in ?mcucr ? mcu control register? on page 65 . 18. updated and moved section ?timer/counter0 prescaler and clock sources?, now located on page 67 . 19. updated ?timer/counter1 initializatio n for asynchronous mode? on page 89 . 20. updated bit description in ?pllcsr ? pll control and status register? on page 97 and ?pllcsr ? pll control and status register? on page 107 . 21. added recommended maximum frequency in ?prescaling and conver- sion timing? on page 129 . 22. updated figure 19-8 on page 134 . 23. updated ?temperature measurement? on page 138 . 24. updated table 19-3 on page 139 .
21 2586js?avr?12/06 attiny25/45/85 9.2 rev. 2586i-09/06 25. updated bit r/w descriptions in: ?timsk ? timer/counter interrupt mask register? on page 84 , ?tifr ? timer/counter interrupt flag register? on page 84 , ?timsk ? timer/counter interrupt mask register? on page 95 , ?tifr ? timer/counter interrupt flag register? on page 96 , ?pllcsr ? pll control and status register? on page 97 , ?timsk ? timer/counter interrupt mask register? on page 106 , ?tifr ? timer/counter interrupt flag register? on page 106 , ?pllcsr ? pll control and status register? on page 107 and ?didr0 ? digital input disabl e register 0? on page 143 . 26. added limitation to ?limitations of debugwire? on page 145 . 27. updated ?dc characteristics? on page 166 . 28. updated table 23-4 on page 170 . 29. updated figure 23-6 on page 173 . 30. updated table 23-7 on page 173 . 31. updated table 24-1 on page 179 . 32. updated table 24-2 on page 179 . 33. updated table 24-26 , table 24-27 and table 24-28 , starting on page 188 . 34. updated table 24-29 , table 24-30 and table 24-31 , starting on page 189 . 35. updated table 24-33 on page 191 . 36. updated table 24-40 , table 24-41 , table 24-42 and table 24-43 , starting on page 195 . 1. all characterization data moved to ?electrical characteristics? on page 166 . 2. all register descriptions are gathered up in seperate sections in the end of each chapter. 3. updated table 13-3 on page 80 , table 13-6 on page 81 , table 13-8 on page 82 and table 22-4 on page 152 . 4. updated ?calibrated internal rc oscillator? on page 27 . 5. updated note in table 8-1 on page 34 . 6. updated ?system control and reset? on page 39 . 7. updated register description in ?i/o ports? on page 53 . 8. updated features in ?usi ? universal serial interface? on page 111 . 9. updated code example in ?spi master operation example? on page 113 and ?spi slave operation example? on page 115 . 10. updated ?analog comparator multiplexed input? on page 123 . 11. updated figure 19-1 on page 127 . 12. updated ?signature bytes? on page 153 . 13. updated ?electrical characteristics? on page 166 .
22 2586js?avr?12/06 attiny25/45/85 9.3 rev. 2586h-06/06 9.4 rev. 2586g-05/06 9.5 rev. 2586f-04/06 9.6 rev. 2586e-03/06 9.7 rev. 2586d-02/06 1. updated ?calibrated internal rc oscillator? on page 27 . 2. updated table 7.12.1 on page 31 . 3. added table 23-1 on page 169 . 1. updated ?internal pll for fast peripheral clock generation - clkpck? on page 23 . 2. updated ?default clock source? on page 25 . 3. updated ?low-frequency crystal oscillator? on page 27 . 4. updated ?calibrated internal rc oscillator? on page 27 . 5. updated ?clock output buffer? on page 30 . 6. updated ?power management and sleep modes? on page 34 . 7. added ?bod disable? on page 34 . 8. updated figure 18-1 on page 123 . 9. updated ?bit 6 ? acbg: analog comparat or bandgap select? on page 124 . 10. added note for table 19-2 on page 129 . 11. updated ?register summary? on page 199 . 1. updated ?digital input enable and sleep modes? on page 57 . 2. updated table 22-15 on page 163 . 3. updated ?ordering information? on page 203 . 1. updated features in ?analog to digital converter? on page 126 . 2. updated operation in ?analog to digital converter? on page 126 . 3. updated table 19-3 on page 139 . 4. updated table 19-2 on page 138 . 5. updated ?errata? on page 209 . 1. updated table 7-4 on page 26 , table 7-5 on page 27 , table 7-9 on page 29 , table 7-12 on page 30 , table 7-11 on page 29 , table 10-1 on page 48 , table 19-4 on page 139 , table 22-15 on page 163 , table 23-5 on page 171 . 2. updated ?timer/counter1 in pwm mode? on page 89 . 3. updated text ?bit 2 - tov1: timer/counter1 overflow flag? on page 96 .
23 2586js?avr?12/06 attiny25/45/85 9.8 rev. 2586c-06/05 9.9 rev. 2586b-05/05 9.10 rev. 2586a-02/05 4. updated values in ?dc characteristics? on page 166 . 5. updated ?register summary? on page 199 . 6. updated ?ordering information? on page 203 . 7. updated rev b and c in ?errata attiny45? on page 210 . 8. all references to power-save mode are removed. 9. updated register adresses. 1. updated ?features? on page 1 . 2. updated figure 1-1 on page 2 . 3. updated code examples on page 17 and page 18 . 4. moved ?temperature measurement? to section 19.9 page 138 . 5. updated ?register summary? on page 199 . 6. updated ?ordering information? on page 203 . 1. clki added, instances of ee mwe/eewe renamed eempe/eepe, removed some tbd. removed ?preliminary description? from ?temperature measurement? on page 138 . 2. updated ?features? on page 1 . 3. updated figure 1-1 on page 2 and figure 9-1 on page 39 . 4. updated table 8-2 on page 38 , table 12-4 on page 64 , table 12-5 on page 64 5. updated ?serial programming instruction set? on page 157 . 6. updated sph register in ?instruction set summary? on page 201 . 7. updated ?dc characteristics? on page 166 . 8. updated ?ordering information? on page 203 . 9. updated ?errata? on page 209 . 1. initial revision.
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